Multiprocessor computer systems consist of nodes interconnected by physical communication links in an n-dimensional topology. Messages between nodes are routed across the physical communication links in a variety of ways. In one approach, such as is described in U.S. Pat. No. 5,970,232, issued Oct. 19, 1999 to Passint et al., routers route messages between pairs of processing element nodes and a three dimensional network. A symmetric eight port router is described that, in one embodiment, has a port connected to each node; the remaining ports are connected to physical communication links in the +X, −X, +Y, −Y, +Z and −Z directions.
A primary consideration in the design of interconnect networks and corresponding routing algorithms is avoiding deadlock. Deadlock occurs when cyclic dependencies arise among a set of channel buffers, causing all involved buffers to fill up and block.
Approaches for avoiding deadlock are often dependent on a regular topology; failure of one or more communication links can reintroduce cyclic dependencies into what had been a deadlock-free routing scheme. What is needed is a system and method of routing that avoids cyclic dependencies in networks with irregular topologies, and in regular topologies made irregular due to failures on one or more components.